A New Gm-C Active Filter with Auto-Tuning Loop Based on PLL Architecture in CMOS Technology
نویسنده
چکیده
In this paper a new Gm-C active filter with auto-tuning loop based on PLL architecture in CMOS technology is presented. The auto-tuning loop of the proposed structure is represented by a PLL having the voltage controlled oscillator implemented with a replica of Gm-C filter in positive feedback connection. The loop sets the biasing of VCO such that the oscillation frequency provided by the loop is equal to the fixed input frequency of the PLL (which represents the centre frequency of the Gm-C core filter). Thus, the loop gives the bias values of the Gm-C core filter in order to maintain its centre frequency equal to the reference frequency at the PLL input, which is independent of process, supply voltage and temperature variations. The proposed 2 order Gm-C Butterworth type band-pass filter provides a ±8% variation of the centre frequency (30MHz) in all critical corners, with a 400mVpp(diff) dynamic range, THD < 1% and uses 1.8V supply voltage. The simulations performed in 65nm CMOS process confirm the theoretical results. Keywords-Auto-tuning Loop; Biquad; CMOS; Gm-C Filter; PLL; Transconductor; VLSI
منابع مشابه
Design of Gate-Driven Quasi Floating Bulk OTA-Based Gm–C Filter for PLL Applications
The advancement in the integrated circuit design has developed the demand for low voltage portable analog devices in the market. This demand has increased the requirement of the low-power RF transceiver. A low-power phase lock loop (PLL) is always desirable to fulfill the need for a low power RF transceiver. This paper deals with the designing of the low power transconductance- capacitance (Gm-...
متن کاملHigh Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
متن کاملA 21.8−27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve −130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier
This paper describes a new approach to low phase noise LC VCO design based on transconductance linearization of the active devices. A prototype 25GHz VCO based on this approach is integrated in a dual loop PLL and achieves superior performance compared to the state of the art. The design is implemented in the 32nm SOI deep sub-micron CMOS technology and achieves a phase noise of −130dBc/Hz at 1...
متن کاملLow-noise and high-frequency clock generation core for VLSI CMOS integration
A new phase-lock loop architecture is proposed to be used as a low-noise and high-frequency clock generation core for VLSI CMOS integration. The novel PLL architecture includes two charge pumps and an active loop filter architecture to implement a dual capacitance multiplication effect, which allows for the implementation of very large loop filter capacitors with very small silicon area. This n...
متن کاملAutomatic Tuning for Linearly Tunable Filters
Automatic Tuning for Linearly Tunable Filters. (May 2004) Sung-Ling Huang, B.S., Tatung Institute of Technology, Taiwan; M.S., Tatung Institute of Technology, Taiwan Chair of Advisory Committee: Dr. Aydin I. Karsilayan A new tuning scheme for linearly tunable high-Q filters is proposed. The tuning method is based on using the phase information for both frequency and Q factor tuning. There is no...
متن کامل